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AN1709 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
PDF  38 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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AN1709 bảng dữ liệu(HTML) 11 Page - STMicroelectronics

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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS
Increasing electrostatic discharges are supplied to every pin of the component until a Latch-up
occurs. Result is the maximum tolerated voltage without Latch-up.
DLU Test methodology and characterization: Electro-Static Discharges (one positive then one
negative test) are applied to each pin of 3 samples when the microcontroller is running to as-
sess the latch-up performance in dynamic mode. Power supplies are set to the typical values,
the oscillator is connected as near as possible to the pins of the microcontroller and the com-
ponent is put in reset mode.
Table 8 shows how the DLU test result is presented in ST datasheets.
Table 8. Example of DLU test Result on ST72F521
1.
Class description: “A” class is an STMicroelectronics internal specification. All its limits are higher
than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC
standard. “B” Class strictly covers all the JEDEC criteria (international standard).
LU/DLU test equipment is same as the one used for the functional EMS (see Figure 1.).
2.1.3 Absolute Electrical Sensitivity
This test is performed to assess the components immunity against destruction caused by
ESD.
Any devices that fails this electrical test program is classified as a failure.
Using automatic ESD tester, Electro-Static Discharges (a positive then a negative pulse sep-
arated by 1 second) are applied to the pins of each sample according to each pin combination.
The sample size depends of the number of supply pins of the device (3 parts*(n+1): n= supply
pins). Two models are usually simulated: Human Body Model (HBM) and Machine Model
(MM). All parts are re-tested on the production tester to verify the static and dynamic parame-
ters still comply with the device datasheet (See Figure 6.).
This test conforms to the JESD22-A114A/A115A standard. See Figure 6. and the following
test sequences.
Symbol
Parameter
Conditions
Class1)
DLU
Dynamic latch-up class
VDD =5V
fOSC=4MHz,
TA=+25°C
A



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