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AN413 bảng dữ liệu(PDF) 14 Page - STMicroelectronics |
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AN413 bảng dữ liệu(HTML) 14 Page - STMicroelectronics |
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14 / 45 page ![]() ST9 basic system configuration AN413 14/45 Doc ID 1875 Rev 2 F5 07 0F ld R#NUM_TDCP,#(LNG_DMA_SCI) F5 06 00 ld R#NUM_TDAP,#(DEPART_DMA_SCI) In this program sequence the DMA transaction counter and Address Pointer register addresses are defined to be R7 and R6 respectively. These two registers are initialized for a block of size 15 bytes starting at register address A0, i.e. R160. 3.8 Timer/watchdog unit configuration Configuration of the Timer/Watchdog requires loading of the 6 registers listed in Table 13, Appendix A. The Timer/Watchdog Control Register, WDTCR, contains a start/stop bit, and is also used to select input, output, and counter modes, as well as input and output enable bits. Example: BC 80 ld wdtcr,#80h In this example the Timer starts counting down in continuous mode, and the input and output sections are disabled. The Wait Control Register, WCR, as well as specifying the number of wait states for access to off-chip program and data memory enables the Watchdog function. Example: CC 40 ld wcr,#wden In this example the Watchdog action is disabled, and the number of wait states are set to zero. The External Interrupt Vector Register, EIVR, contains a bit, TLIS, which is used to control the Top Level Interrupt source (Timer/Watchdog EOC or External NMI). A second bit IAOS is used to select the Timer/Watchdog as an interrupt source on channel A0 (INT0). This register is also used to supply the 4 most significant bits of the External Interrupt Vector. Example: 6C 20 ld eivr,#EXT_IT_VECT In this example the Timer/Watchdog EOC generates an interrupt on channel A0 at each End of Count. The Top Level Interrupt is isolated from the NMI input and may be used for a Software Trap. The Timer/Watchdog Prescaler Register, WDTPR, contains an 8-bit value which is loaded into the Prescaler register. Example: 90 DA clr wdtpr The specified Prescaler value of zero leads to a minimum timer count period of 333ns, assuming a system clock running at 12MHz. The Timer/Watchdog High Register, WDTHR, and Timer/Watchdog Low Register, WDTLR, together contain a 16-bit value which is loaded into the counter at each End of Count. Example: BF F8 0B BB ldw WDTR,#3003 |
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