AN413 datasheet(12/45 Pages) STMICROELECTRONICS

12 / 45 page

ST9 basic system configuration

AN413

12/45

Doc ID 1875 Rev 2

The Baud Rate Generator Register, BRGR, specifies a 16-bit division ratio.

Example:

BF DC 00 4E ldw s_brgr,#DIV_9600

This example specifies a division ratio yielding 9600 Bauds with a 24 Mhz external clock.

Writing to a Baud Rate Generator Register immediately disables and resets both the SCI

Baud Rate generator, the transmitter and receiver circuitry. After writing to the remaining

Baud Rate Generator Register, the transmitter and receiver circuits are enabled. The Baud

Rate Generator will load the new value and start counting.

To initialize the SCI, user should first initialize one Baud Rate Generator Divisor Register.

This will reset all SCI circuitry. Initialize all other SCI registers for the desired operating

mode. To enable the SCI, initialize the remaining Baud Rate Generator Register.

The Address Compare Register, ACR, contains an 8-bit value which may be used as a

match against which a received address may be tested to set the Receive Address Pending

bit.

Example:

5C 0D ld s_acr,#RETURN

This will cause the Receive Address Pending bit to be set if an End of Command character

bit-pattern is received.

The Interrupt Vector Register, IVR, defines the most significant 5 bits of the vector table byte

address. It thus points to the first of four vector table word address entries.

Example:

4C 00x ld s_ivr,#SCI_IT

In this example, after the external symbol has been linked in, the Vector Table entry address

will be loaded into IVR at execution time.

The Interrupt Mask Register, IMR, contains five interrupt masking bits and two End of Block

DMA status bits. It also selects the shift register or holding register as source of the

transmitter register empty interrupt.

Example:

6C 05 ld s_imr,#00000101b

In this example the interrupt pending bits are reset, the Transmitter data interrupt is masked,

and the Receiver data, data error, and address interrupts are unmasked.

The Interrupt/DMA Priority Register, IDPR, specifies the Interrupt/DMA priority, selects one

of four Address modes, and controls the emission of Break characters and enables

address/9th bit data mode. It also provides mask bits for Receive and Transmit DMA

transfers.

Example:

9C 04 ld s_idpr,#04h

In this example a priority level of 4 is specified, and Transmitter DMA requests are masked.

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