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AN3161 bảng dữ liệu(PDF) 5 Page - STMicroelectronics |
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AN3161 bảng dữ liệu(HTML) 5 Page - STMicroelectronics |
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5 / 14 page ![]() AN3161 Saturation voltage impact on parallel Doc ID 17151 Rev 1 5/14 Figure 2. ∆IC (@TJ > 25 °C) of two paralleled IGBT without negative feedback As a consequence of the negative VCE(sat) coefficient, a higher ∆IC is established at high TJ (Figure 2). This can cause thermal instability if an accurate negative feedback is not implemented. NPT and field stop IGBTs have positive VCE(sat) coefficients (the latter typically starting from low current levels). When working in parallel the one carrying the higher current increases its temperature, which causes a VCE(sat) increase. This means that, at the same on-state voltage level, the current does not increase with temperature as in PT IGBTs; this guarantees an intrinsic balancing mechanism, preventing thermal runaway. AM06440v1 Tj>25°C, V GE =15V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 Vce collector emitter voltage (V) ΔIC IC1 VCE1=VCE2 ICTOT=IC(T1)+IC(T2) IC2 |
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