AN2846 datasheet(17/35 Pages) STMICROELECTRONICS

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AN2846

Application guidelines

Doc ID 15130 Rev 1

17/35

1.4.4

SPI functionality

At the /CS falling edge the following operations are done:

●

The input data states, parity and control bits are frozen and stored in the data and

control shift registers.

●

The MSB (Bit 15) is shifted out first to MISO.

The SCLT3-8 data transfer uses SPI protocol with CPOL = 0, CPHA = 0 conditions. This

means the SCK signal must be at low level state when the /CS is falling (communication

starts). In this case the MSB (bit15) is transferred first from MISO as soon as /CS falls, and

all the remaining bits are transferred at each SCK falling edge.

Figure 25.

SCK and /CS synchronization security

For more flexibility the SPI protocol has been enhanced and takes into account the case

where SCK signal is at high level when /CS falls to low level. In this case, as previously the

MSB will be present at MISO pin at the /CS falling edge but the following bit will be available

only at the second SCK falling edge.

In both cases the rule is: a rising SCK edge must occur after the falling /CS edge to validate

the first SCK falling edge. Otherwise the state change duration of MISO may be too short to

correctly trigger the transmission of the MSB (bit 15) (see Figure 25).

In normal operation the two last bits are 0 and 1 indicating the end of the transmission.

The data transmission runs as long as the /CS is at low state. As soon as /CS returns to

high level, the data transfer is disabled and the MISO output is in high impedance - hi-Z.

When MOSI input is used in daisy chain operation, the inputs are captured at each SCK

rising edge and loaded into the shift register. Loaded data has no effect on the SCLT3-8.

Figure 26.

16-bit transmission example

MISO

/CS

SCK

MISO

/CS

SCK

Bit14

MISO

/CS

SCK

Bit14

SCK is low when /CS falls

SCK is high when /CS falls

/CS

SCK

MISO

B15

B8 B7

Input data bits

Control bits

10 1

1 1

0 1

10 1

1 1

0 1

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