AN3308 datasheet(35/52 Pages) STMICROELECTRONICS

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AN3308

Click and double click recognition

Doc ID 18198 Rev 1

35/52

8.3.6

TIME WINDOW (3Dh)

1 LSB = 1/ODR.

TW7 throughTW0 define the maximum interval of time that can elapse after the end of the

latency interval in which the click detection procedure can start, in cases where the device is

configured for double click detection.

8.3.7

CTRL_REG3 [Interrupt CTRL register] (22h)

8.4

Examples

The following figures show the click interrupt generation in different conditions. The

illustrations have been captured on a PC running the demonstration kit GUI interface with

ODR set to 400 Hz and full scale to 4 g. The content of the LIS3DH registers have been

modified via the dedicated panel of the software interface that allows the user to evaluate all

the different settings and features of the click embedded function. In the following examples,

only the X axis has been enabled for the click interrupt generation.

Table 29.

TIME_WINDOW description

TW7

TW6

TW5

TW4

TW3

TW2

TW1

TW0

Table 30.

TIME_LATENCY description

TW7-TW0

Tap-Tap Time Window

Table 31.

CTRL_REG3 register

I1_TAP

I1_INT1

I1_DRDY1

I1_DRDY2

I1_WTM

I1_OVERRUN

Table 32.

CTRL_REG3 description

I1_TAP

Tap interrupt on INT1. Default value 0.

(0: disable; 1: enable)

I1_INT1

Interrupt generator 1 on INT1 pin. Default value 0.

(0: disable; 1: enable)

I1_DRDY1

DRDY1 interrupt on INT1. Default value 0.

(0: disable; 1: enable)

I1_DRDY2

DRDY2 interrupt on INT1. Default value 0.

(0: disable; 1: enable)

I1_WTM

FIFO watermark interrupt on INT1. Default value 0.

(0: disable; 1: enable)

I1_OVERRUN

FIFO overrun interrupt on INT1. Default value 0.

(0: disable; 1: enable)

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