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AN3142 bảng dữ liệu(PDF) 24 Page - STMicroelectronics |
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AN3142 bảng dữ liệu(HTML) 24 Page - STMicroelectronics |
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24 / 44 page ![]() Designing a fixed-off-time PFC AN3142 24/44 Doc ID 17005 Rev 3 A complete description is given by the diagram in Figure 14 and 15 which shows the typical multiplier characteristics family. The linear operation of the multiplier is guaranteed within the range 0 to 3 V of VMULT and the range 0 to 1.16 V (typ.) of Vcs, while the minimum guaranteed value of the maximum slope of the characteristics family (typ.) is: Equation 48 The voltage on the MULT pin is used also to derive the information on the RMS mains voltage for the VFF compensation. The suggested procedure to properly set the operating point of the multiplier is now described. First, the maximum peak value for VMULT, VMULTmax is selected. This value, which occurs at maximum mains voltage, should be 3 V or thereabouts in wide range mains and less in the case of single mains. The sense resistor selected is Rs = 0.12 Ω and it is described in the pin #4 section. According to the L6563S datasheet and to the linearity setting of the pin, the maximum voltage accepted on the multiplier input is: Where ILpk and Rs have been already calculated, 1.66 is the Multiplier maximum slope, reported on the datasheet. From 15 the maximum required divider ratio is calculated as: Equation 49 Figure 14. Multiplier characteristics family for VFF =1 V Figure 15. Multiplier characteristics family for VFF=3 V Multiplier Char ac ter istics @ VFF=1 V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 0 0 .1 0 .2 0.3 0.4 0 .5 0.6 0.7 0 .8 0.9 1 1.1 VMU LT (V) 4.5V 3.5V Uppe r voltage clamp 3. 0V 2. 6V 5.0V 4.0V 5.5 VC OMP Multiplier characteristics @VFF = 3V 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 00 .5 1 1.522.5 33.5 VMU LT (V ) 2.6V 3.0V 4.5V 4.0V 3.5V 5.0V 5.5V Upper voltage VCOMP V V 66 . 1 dV dV MULT CS = V 3 VMULT max = (15) ` 10 8 Vac 265 2 V 00 . 3 VAC 2 V k 3 max max MULT p − ⋅ = ⋅ = ⋅ = |
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