AN3112 datasheet(21/36 Pages) STMICROELECTRONICS

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AN3112

Designing a fixed-off-time PFC

Doc ID 16820 Rev 3

21/36

a current from the output bus which needs to be significantly higher than the current biasing

the error amplifier and PFC_OK comparator.

The OVP function described above can handle "normal" over-voltage conditions, that is,

those resulting from an abrupt load/line change or occurring at start-up. If the over-voltage is

generated by a feedback disconnection for instance, when one of the upper resistors of the

output divider fails to open, an additional circuitry detects the voltage drop of pin INV. If the

voltage on pin INV is lower than 1.66V (Typ.) and at same time the OVP is active, a feedback

failure is assumed.

Therefore, the gate drive activity is immediately stopped, the device is shut down, its

quiescent consumption is reduced to below 180 µA and the condition is latched as long as

the supply voltage of the IC is above the UVLO threshold. To restart the system it is

necessary to recycle the input power, so that the Vcc voltage of the L6564 goes below 6 V

and that one of the PWM controllers goes below its UVLO threshold. Note that this function

offers complete protection against feedback loop failures or erroneous settings, and also

against the failure of the protection itself. Either resistor of the PFC_OK divider failing short

or open or a PFC_OK pin floating may result in shutting down the IC and stopping the pre-

regulator. In addition, the PFC_OK pin doubles its function as a not-latched IC disable: a

voltage below 0.23 V shuts down the IC, reducing its consumption below 2 mA. To restart

the IC, simply let the voltage at the pin go above 0.27 V.

Pin 2 (COMP): This pin is the output of the E/A that is fed into one of the two inputs of the

multiplier. A feedback compensation network is placed between this pin and the INV pin

(pin#1). It must be designed with a narrow bandwidth in order to avoid the system rejecting

the output voltage ripple (100 Hz) that would cause high distortion of the input current

waveform. A theoretical criterion to define the compensation network value is to set the E/A

bandwidth (BW) from 20 to 30 Hz.

For a more complex way of compensating the FOT PFC please refer to [

1], [2], [3].

A compensated two-pole feedback network for this 400 W FOT PFC can be obtained with

the following values:

to which the following open-loop transfer function and its phase function correspond.

100

compP =

compS

Ω

compS

(14)

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