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AN3112 bảng dữ liệu(PDF) 13 Page - STMicroelectronics

tên linh kiện AN3112
Giải thích chi tiết về linh kiện  Solution for designing a fixed off-time controlled PFC pre-regulator
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AN3112
Designing a fixed-off-time PFC
Doc ID 16820 Rev 3
13/36
Equation 18
Equation 19
The power dissipated on a D15XB60 bridge may be:
Equation 20
4.3.2
Input capacitor
The input filter capacitor (Cin) is placed across the diode bridge output. This capacitor must
smooth the high-frequency ripple and must sustain the maximum instantaneous input
voltage. In a typical application an EMI filter is placed between the mains and the PFC
circuit. In this application the EMI filter is reinforced by a differential mode Pi-filter after the
bridge to reject the differential noise coming from the whole switching circuit. The design of
the EMI filter (common mode and differential mode) is not described here. The value of the
input filter capacitor can be calculated as follows, simply considering the output power that
the PFC should deliver at full load:
Equation 21
The maximum value of this capacitor is limited to avoid line current distortion. The value
chosen for this design is 1 µF.
4.3.3
Output capacitor
The output bulk capacitor (Co) selection depends on the DC output voltage
(4), the allowed
maximum voltage
(7) and the converter output power (3).
The 100/120 Hz (twice the mains frequency) voltage ripple (Vout = peak-to-peak ripple
value)
(8) is a function of the capacitor impedance and the peak capacitor current:
Equation 22
With a low ESR capacitor the capacitive reactance is dominant, therefore:
A
53
.
3
2
A
99
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4
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avg
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th
inrms
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diode
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53
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out
3
in
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10
5
.
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∆



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