AN3095 datasheet(47/55 Pages) STMICROELECTRONICS

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AN3095

Experimental results

Doc ID 16555 Rev 3

47/55

The PWM embedded peripheral used for the DC-AC stage is configured to generate a

triangular carrier at 17.4 kHz with a resolution of 16,6 ns and programmable dead-time

insertion to avoid cross-conduction. For the sake of security the complementary pairs must

be disabled synchronously in the case of power stage failure/fault (e.g. overcurrent) and this

is performed by a dedicated emergency stop input embedded in the peripheral.

Inverter output voltage and current are shown in Figure 36, 37, 38 and 39 at different power

levels and both in standalone and grid-connected operation. The efficiency of the DC-DC

converter and overall system is shown in Figure 40 and 41, with different values of input

voltage. Further improvements in terms of efficiency are possible using the hybrid inverter

topology (two low frequency IGBTs and two high frequency MOSFETs). In this case the

modulating strategy controlling the high-side devices (MOSFETs) and the low-side devices

(IGBTs) must be modified according to the information in Figure 42 and 43, where the

modulation used for the high-side and low-side devices is shown. The proposed converter

performs with a power factor value higher than 90 % for any power level above 1 % of

Figure 32.

DC-DC phase-shift modulation

Figure 33.

Phase-shifted signals, transformer

current in CCM, power MOSFET M1

drain current

Figure 34.

Power MOSFET M1- Ch1 gate

signal; Ch2 drain-source voltage

and drain current Ch4

Figure 35.

Phase-shifted gate signals (Ch1,

Ch2), primary and secondary

transformer voltage (Ch3, Ch4)

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