ICL7109CPL datasheet(12/25 Pages) INTERSIL

12 / 25 page

converter. When the MODE pin is low or left open (this input

is provided with a pulldown resistor to ensure a low level

when the pin is left open), the converter is in its “Direct” out-

put mode, where the output data is directly accessible under

the control of the chip and byte enable inputs. When the

MODE input is pulsed high, the converter enters the UART

handshake mode and outputs the data in two bytes, then

returns to “direct” mode. When the MODE input is left high,

the converter will output data in the handshake mode at the

end of every conversion cycle. (See section entitled “Hand-

shake Mode” for further details).

STATUS Output

During a conversion cycle, the STATUS output goes high at

the beginning of Signal Integrate (Phase II), and goes low

one-half clock period after new data from the conversion has

been stored in the output latches. See Figure 3 for of this tim-

ing. This signal may be used as a “data valid” flag (data never

changes while STATUS is low) to drive interrupts, or for

monitoring the status of the converter.

RUN/HOLD Input

When the RUN/HOLD input is high, or left open, the circuit will

continuously perform conversion cycles, updating the output

latches after zero crossing during the Deintegrate (Phase III)

portion of the conversion cycle (See Figure 3). In this mode of

operation, the conversion cycle will be performed in 8192

clock periods, regardless of the resulting value.

FIGURE 4. DIGITAL SECTION

TEST

LATCH

CLOCK

POL OR

12 11 10 9

5432

10 11 12 13 14 15 16

226

STATUS

RUN/

OSC OSC OSC BUF MODE

SEND

HOLD

IN OUT SEL OSC

OUT

LOW ORDER

BYTE OUTPUTS

BBB

BBB BB

GND

LBEN

HBEN

CE/LOAD

ANALOG

SECTION

COMP OUT

INT

DEINT (+)

DEINT (-)

CONVERSION

CONTROL LOGIC

OSCILLATOR

AND CLOCK

CIRCUITRY

HIGH ORDER

BYTE OUTPUTS

12-BIT COUNTER

14 LATCHES

14 THREE-STATE OUTPUTS

HANDSHAKE

LOGIC

ICL7109

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