CDP1805ACE datasheet(16/30 Pages) INTERSIL

tên linh kiện	CDP1805ACE

Giải thích chi tiết về linh kiện	CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer

PDF	30 Pages

Scroll/Zoom	100%

nhà sản xuất	INTERSIL [Intersil Corporation]

Trang chủ	http://www.intersil.com/cda/home

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16 / 30 page

State Transitions

The CDP1805A and CDP1806A state transitions are shown

in Figure 13. Each machine cycle requires the same period

of time, 8 clock pulses, except the initialization cycle (INlT)

which requires 9 clock pulses. Reset is asynchronous and

can be forced at any time.

FIGURE 12A. TPA PAUSE TIMING

NOTE:

9. Pause (in clock waveform) while represented here as one clock

cycle in duration, could be infinitely long.

FIGURE 12B. TPB PAUSE TIMING

FIGURE 12. PAUSE MODE TIMING WAVEFORMS

PAUSE

ENTER

PAUSE

RESUME

RUN

tPLH

tPHL

tSU tH

tSU

CLOCK

TPA

WAIT

ENTER

PAUSE

RESUME

RUN

PAUSE

tPLH

tPHL

tSU tH

tSU

CLOCK

TPB

WAIT

S1 RESET

PAUSE

S1 EXECUTE

RESET

DMA + INT

S1 INIT

DMA

• FORCE S1

INT

• DMA • RESET

IDLE

• DMA • INT

FORCE S1

(LONG BRANCH,

LONG SKIP, NOP, RSXD, ETC)

S2 DMA

DMA

SO FETCH

DMA

• INT

“68”

S3 INT

FORCE S0

DMA

• IDLE • INT

• FORCE S1

FORCE S0

DMA

INT

• DMA • FORCE S1

PRIORITY:

RESET

FORCE S0, S1

DMA IN

DMA OUT

INT

FIGURE 13. STATE TRANSITION DIAGRAM

INT

• DMA

CDP1805AC, CDP1806AC

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