E28F002BVB80 datasheet(39/55 Pages) INTEL

39 / 55 page

2-MBIT SmartVoltage BOOT BLOCK FAMILY

SEE NEW DESIGN RECOMMENDATIONS

NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to

Characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally

which includes verify and margining operations.

3. Refer to command definition table for valid A

IN. (Table 7)

4. Refer to command definition table for valid D

IN. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).

6. For boot block program/erase, RP# should be held at V

HH or WP# should be held at VIH until operation completes

successfully.

7. Time t

PHBR is required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See

Test Configuration (Figure 14), 3.3 V Standard Test component values.

10. See

Test Configuration (Figure 14), 5 V High-Speed Test component values.

11. See

Test Configuration (Figure 14), 5 V Standard Test component values.

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

6.5V

WHEH

WHWL

Valid

SRD

WHQV1,2,3,4

PHHWH

PHWL

High Z

WHDX

(V)

PPH

PPLK

PPH

WP#

AVAV

AVWH

WHAX

DVWH

WLWH

QVPH

QVVL

VPWH

ELWL

NOTES:

1. VCC Power-Up and Standby.

2. Write program or Erase Set-Up Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

0530_17

Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)

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