E28F002BVB80 datasheet(21/55 Pages) INTEL

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2-MBIT SmartVoltage BOOT BLOCK FAMILY

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3.3.2.1

Clearing the Status Register

The WSM sets status bits 3 through 7 to “1,” and

clears bits 6 and 7 to “0,” but cannot clear status

bits 3 through 5 to “0.” Bits 3 through 5 can only be

cleared by the controlling CPU through the use of

the Clear Status Register (50H) command, because

these bits indicate various error conditions. By

allowing the system software to control the resetting

of these bits, several operations may be performed

(such as cumulatively programming several bytes

or erasing multiple blocks in sequence) before

reading the status register to determine if an error

occurred during that series. Clear the status register

before beginning another command or sequence.

Note, again, that a Read Array command must be

issued before data can be read from the memory or

intelligent identifier.

3.3.3

PROGRAM MODE

Programming

executed

using

two-write

sequence. The Program Set-Up command is written

to the CUI followed by a second write which

specifies the address and data to be programmed.

The WSM will execute a sequence of internally

timed events to:

Program the desired bits of the addressed

memory word or byte.

Verify that the desired bits are sufficiently

programmed.

Programming of the memory results in specific bits

within a byte or word being changed to a “0.”

If the user attempts to program “1”s, there will be no

change of the memory cell content and no error

occurs.

The status register indicates programming status:

while the program sequence is executing, bit 7 of

the status register is a “0.” The status register can

be polled by toggling either CE# or OE#. While

programming, the only valid command is Read

Status Register.

When programming is complete, the program status

bits

should be checked.

the

programming

operation was unsuccessful, bit 4 of the status

If bit 3 is set to a “1,” then VPP was not within

acceptable limits, and the WSM did not execute the

programming sequence.

The status register should be cleared before

attempting the next operation. Any CUI instruction

can

after

programming

completed;

however, reads from the memory array or intelligent

identifier cannot be accomplished until the CUI is

given the appropriate command.

3.3.4

ERASE MODE

To erase a block, write the Erase Set-Up and Erase

Confirm commands to the CUI, along with the

addresses identifying the block to be erased. These

addresses are latched internally when the Erase

Confirm command is issued. Block erasure results

in all bits within the block being set to “1.” Only one

block can be erased at a time.

The WSM will execute a sequence of internally

timed events to:

Program all bits within the block to “0.”

Verify

that

all

bits

within

the

block

are

sufficiently programmed to “0.”

Erase all bits within the block to “1.”

Verify

that

all

bits

within

the

block

are

sufficiently erased.

While the erase sequence is executing, bit 7 of the

status register is a “0.”

When the status register indicates that erasure is

complete, check the erase status bit to verify that

the erase operation was successful. If the erase

operation was unsuccessful, bit 5 of the status

Failure. If VPP was not within acceptable limits after

the Erase Confirm command is issued, the WSM

will not execute an erase sequence; instead, bit 5 of

the status register is set to a “1” to indicate an

Erase Failure, and bit 3 is set to a “1” to identify that

VPP supply voltage was not within acceptable limits.

Clear the status register before attempting the next

operation. Any CUI instruction can follow after

erasure is completed; however, reads from the

memory

array,

status

intelligent

identifier cannot be accomplished until the CUI is

given the Read Array command.

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