GDC21D301A datasheet(19/35 Pages) HYNIX

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GDC21D301A

VPWM control (0x012)

The chip uses Sigma-delta modulation for VPWM

signal.

Modulation

clock

1/34

system

clock(27MHz/34 = 794KHz). VPWM output signal

is generated by this value. When the register value

is 0x7FFF, the period of '1' and the period of '0'

have the same value of 0.630usec, and the cycle

time is 1.259usec, i.e., the duration of VPWM

output signal is 50%. The larger is the value greater

than 0x7FFF, the longer is the high period

generated. For example, if register value is 0x0000,

there is no data of '1' in 65536 data. Only the data

of '0' is almost uniformly distributed in 65536 data.

Adjusting PWM pulse, system VCXO can be

controlled to achieve lip synchronization or system

clocks locking.

FIELD

BITS

DESCRIPTION

VALUES

DEFAULT

VPWM

15:0

Video PWM control

0x0000 to 0xFFFF

0x7FFF

Sync Hysteresis (0x014)

FIELD

BITS

DESCRIPTION

VALUES

DEFAULT

Scd

7:5

Sync Drop

0 = should not be used

1 – 7 = The number of consecutive

sync bytes must be discarded to

constitute a sync drop.

0x1

Scl

4:0

Sync Lock

0 = should not be used

1 – 31 = The number of consecutive

sync bytes must be detected

before sync is acquired.

0x03

Scd

Scl

VPWM

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