ATXMEGA8E5_14 datasheet(42/147 Pages) ATMEL

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XMEGA E5 [DATASHEET]

Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014

22.

TWI – Two Wire Interface

22.1

Features

One two-wire interface

Phillips I2C compatible

System Management Bus (SMBus) compatible

Bus master and slave operation supported

Slave operation

Single bus master operation

Bus master in multi-master bus environment

Multi-master arbitration

Bridge mode with independent and simultaneous master and slave operation

Flexible slave address match functions

7-bit and general call address recognition in hardware

10-bit addressing supported

Address mask register for dual address match or address range masking

Optional software address recognition for unlimited number of addresses

Slave can operate in all sleep modes, including power-down

Slave address match can wake device from all sleep modes

100kHz, 400kHz and 1MHz bus frequency support

Slew-rate limited output drivers

Input filter for bus noise and spike suppression

Support arbitration between start/repeated start and data bit (SMBus)

Slave arbitration allows support for address resolve protocol (ARP) (SMBus)

Supports SMBUS Layer 1 timeouts

Configurable timeout values

Independent timeout counters in master and slave (Bridge mode support)

22.2

Overview

The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus

(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.

A device connected to the bus must act as a master or a slave. One bus can have many slaves and one or several

masters that can take control of the bus.

The TWI module supports master and slave functionality. The master and slave functionality are separated from each

other, and can be enabled and operate simultaneously and separately. The master module supports multi-master bus

operation and arbitration. It contains the baud rate generator. Quick command and smart mode can be enabled to auto-

trigger operations and reduce software complexity. The master can support 100kHz, 400kHz and 1MHz bus frequency.

The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is

also supported. A dedicated address mask register can act as a second address match register or as a register for

address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables

the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address

matching to let this be handled in software instead. By using the bridge option, the slave can be mapped to different pin

locations. The master and slave can support 100kHz, 400kHz and 1MHz bus frequency.

The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,

and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave

modes.

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