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ATXMEGA8E5 bảng dữ liệu(PDF) 19 Page - ATMEL Corporation |
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ATXMEGA8E5 bảng dữ liệu(HTML) 19 Page - ATMEL Corporation |
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19 / 147 page  19 XMEGA E5 [DATASHEET] Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014 Figure 10-1. Event system overview and connected peripherals. The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow up to eight parallel event configurations and routing. The maximum routing latency of an external event is two peripheral clock cycles due to re-synchronization, but several peripherals can directly use the asynchronous event without any clock delay. The event system works in all power sleep modes, but only asynchronous events can be routed in sleep modes where the system clock is not available. Timer / Counters ADC Real Time Counter CPU / Software EDMA Controller IRCOM Event Routing Network Event System Controller clkPER Prescaler AC Port Pins DAC XMEGA Custom Logic |
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