HT47C20 datasheet(12/56 Pages) HOLTEK

12 / 56 page

HT47C20

January 18, 2000

converter control register (ADCR; 25H). The re-

maining space before the 40H are reserved for fu-

ture expanded usage and reading these location

will return the result 00H. The general purpose

data memory, addressed from 40H to 7FH, is

used for data and control information under in-

struction command.

All data memory areas can handle arithme-

tic, logic, increment, decrement and rotate

operations. Except for some dedicated bits,

each bit in the data memory can be set and re-

set by the SET [m].i and CLR [m].i instruc-

tion, respectively. They are also indirectly

accessible through memory pointer registers

(MP0;01H, MP1;03H).

Indirect addressing register

Location 00H and 02H are indirect addressing

registers that are not physically implemented.

Any read/write operation of [00H] and [02H] ac-

cess data memory pointed to by MP0 (01H) and

MP1 (03H) respectively. Reading location 00H

or 02H indirectly will return the result 00H.

Writing indirectly results in no operation.

The function of data movement between two in-

direct addressing registers are not supported.

The memory pointer registers, MP0 and MP1,

are both 8-bit registers which can be used to ac-

cess the data memory by combining correspond-

ing indirect addressing registers.

Only MP0 can be applied to data memory, while

MP1 can be applied to data memory and LCD

display memory.

Accumulator

The accumulator is closely related to ALU op-

erations. It is also mapped to location 05H of

the data memory and is capable of carrying out

immediate data operations. The data move-

ment between two data memory locations

must pass through the accumulator.

G ene r a l P u r p os e

D a t a M em or y

( 64 B y t e s )

7F H

20H

IN T C 1

TM R A H

TM R A L

TM R C

TM R B H

TM R B L

AD C R

21H

22H

23H

24H

25H

26H

40H

S pec i a l P u r pos e

D a t a M em or y

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0A H

0B H

0C H

0D H

0EH

0F H

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1A H

1B H

1C H

1D H

1EH

1F H

: U n u s e d

R ead as " 0 0 "

I ndi r e c t A ddr es s i ng R egi s t er 0

MP 0

MP 1

AC C

PC L

TB L P

TB L H

RT CC

ST AT U S

IN T C 0

I ndi r e c t A ddr es s i ng R egi s t er 1

RAM mapping (bank 0)

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