ML7344J datasheet(128/151 Pages) ETC2

128 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

128/151

(2) TX FIFO access error

If one of the following conditions is met, TX FIFO access error interrupt (INT[20]: group3) will be generated.

●After TX Data request accept completion interrupt (INT[17]: group3] was generated, next packet is written

to the TX_FIFO without transmiting the current TX data.

●Data write overflow occurs to the TX_FIFO.

●No TX data in the TX_FIFO during TX data transimission.

When TX FIFO acccess error interrupt occurs, issuing TRX_OFF after TX completion interrupt (INT[16]:

group3) is recognized, or issueing Force_TRX_OFF by [RF_STATUS:B0 0x0A] register without waiting for TX

completion interrupt. After that, issuing TX FIFO pointer clear by [STATE_CLR:B0 0x16] register and clear

remaining interrupts relative with TX in the [INT_SOURCE_GRP3:B0 0x0F] register.

If TX FIFO access error occurs, subquent TX data will be inverted. CRC error should be detected at rexeiver

side even if TRX_OFF is issued when TX completion interrupt detected.

START

FAST_TX setting

[RF_STATUS_CTRL:B0 0x0A]

[TXFIFO_THRH/L:B0 0x17/18]

Yes

Next packet TX ?

Yes

TRX_OFF issue

[RF_STATUS:B0 0x0B]

TX FIFO access error (INT[20])?

[NT_SOURCE_GRP3:B0 0x0F(4)]

Normal TX

(To TX flowchart)

Yes

TX completion (INT[16]) ?

[INT_SOURCE_GRP3:B0 0x0F(0)]

Forced to stop TX ?

Force_TRX_OFF issue

[RF_STATUS:B0 0x0B]

TX FIFO pointer clear

[STATE_CLR:B0 0x16(0)]

Clear INT GRP3

INT[16]-[20]

[INT SOURCE GRP3:B0 0x0F]

RF state transition wait flow

Write TX data *1

[WR_TX_FIFO:B0 0x7C]

*1 If data written to FIFO exceed THFIFO_THRL[5:0]

[TXFIFO_THRL:B0 0x18(5-0)]+1, TX will start.

(Length is included in the data length written to

FIFO)

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