ML7344J datasheet(110/151 Pages) ETC2

110 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

110/151

●TX Sequence

(1) DIO mode

DIO(TX) mode can be selected by setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b01 or 0b10. In

DIO mode, when TX_ON is issued, data input on the pin related DIO will be transimitted to the air. After TX

completion, TRX_OFF should be issued.

*3: Timing up to DCLK output varies depending on

TX preamble, SFC, data rate.

*2: preamble/SyncWord is transmitted based on the

following registers.

Preamble

[DATA_SET1: B0 0x07]

[TXPR_LEN_H/L: B0 0x42-43]

SyncWord

[SYNCWORD1_SET0-3: B1 0x27-2A]

[SYNCWORD2_SET0-3: B1 0x2B-2E]

[SYNC_WORD_LEN: B1 0x25]

[DATA_SET2: B0 0x08]

*4: TX data must be input at falling edge of DCLK.

*1 DIO/DCLK pins are defined as follows:

[GPIO0_CTRL: B0 0x4E]

[GPIO1_CTRL: B0 0x4F]

[GPIO2_CTRL: B0 0x50]

[GPIO3_CTRL: B0 0x51]

[EXT_CLK_CTRL: B0 0x52]

[SPI/EXT_PA_CTRL: B0 0x53]

*5: Please refer to RF state transition wait flow.

Preamble/SyncWord setting *2

START

TX_ON issue

[RF_STATUS: B0 0x0B]

END

TX completed?*5

Yes

TRX_OFF issue

[RF_STATUS: B0 0x0B]

TX data input *4

(DIO pins)

Yes

Next packet to be transmitted?

TXDIO_CTRL setting=0b10

[DIO_SET: B0 0x0C(5-4)]

DIO pins setting *1

DCLK output wait *3

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