A3P030 datasheet(76/210 Pages) MICROSEMI

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ProASIC3 Flash Family FPGAs

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Table 2-97 • Parameter Definition and Measuring Nodes

Parameter Name

Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ

Clock-to-Q of the Output Data Register

HH, DOUT

tOSUD

Data Setup Time for the Output Data Register

FF, HH

tOHD

Data Hold Time for the Output Data Register

FF, HH

tOSUE

Enable Setup Time for the Output Data Register

GG, HH

tOHE

Enable Hold Time for the Output Data Register

GG, HH

tOCLR2Q

Asynchronous Clear-to-Q of the Output Data Register

LL, DOUT

tOREMCLR

Asynchronous Clear Removal Time for the Output Data Register

LL, HH

tORECCLR

Asynchronous Clear Recovery Time for the Output Data Register

LL, HH

tOECLKQ

Clock-to-Q of the Output Enable Register

HH, EOUT

tOESUD

Data Setup Time for the Output Enable Register

JJ, HH

tOEHD

Data Hold Time for the Output Enable Register

JJ, HH

tOESUE

Enable Setup Time for the Output Enable Register

KK, HH

tOEHE

Enable Hold Time for the Output Enable Register

KK, HH

tOECLR2Q

Asynchronous Clear-to-Q of the Output Enable Register

II, EOUT

tOEREMCLR

Asynchronous Clear Removal Time for the Output Enable Register

II, HH

tOERECCLR

Asynchronous Clear Recovery Time for the Output Enable Register

II, HH

tICLKQ

Clock-to-Q of the Input Data Register

AA, EE

tISUD

Data Setup Time for the Input Data Register

CC, AA

tIHD

Data Hold Time for the Input Data Register

CC, AA

tISUE

Enable Setup Time for the Input Data Register

BB, AA

tIHE

Enable Hold Time for the Input Data Register

BB, AA

tICLR2Q

Asynchronous Clear-to-Q of the Input Data Register

DD, EE

tIREMCLR

Asynchronous Clear Removal Time for the Input Data Register

DD, AA

tIRECCLR

Asynchronous Clear Recovery Time for the Input Data Register

DD, AA

Note:

*See Figure 2-15 on page 2-70 for more information.

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