ADF7021 datasheet(61/64 Pages) AD

61 / 64 page

Data Sheet

ADF7021

Rev. B | Page 61 of 64

Rx_TEST_

MODES

Tx_TEST_

MODES

Σ-Δ_TEST_

MODES

PLL_TEST_

MODES

ANALOG_TEST_

MODES

CLK_-MUX

ADDRESS

BITS

ANALOG TEST MODES

BAND GAP VOLTGE

40µA CURRENT FROM REG4

FILTER I CHANNEL: STAGE 1

FILTER I CHANNEL: STAGE 2

FILTER I CHANNEL: STAGE 1

FILTER Q CHANNEL: STAGE 1

FILTER Q CHANNEL: STAGE 2

FILTER Q CHANNEL: STAGE 1

ADC REFERENCE VOLTAGE

BIAS CURRENT FROM RSSI 5µA

FILTER COARSE CAL OSCILLATOR O/P

ANALOG RSSI I CHANNEL

OSET LOOP +VE FBACK V (I CH)

SUMMED O/P OF RSSI RECTIFIER+

SUMMED O/P OF RSSI RECTIFIER–

BIAS CURRENT FROM BB FILTER

Rx TEST MODES

NORMAL

SCLK, SDATA -> I, Q

REVERSE I,Q

LINEAR SLICER ON RXDATA

CORRELATOR SLICER ON TxRxDATA

ADDITIONAL FILTERING ON I, Q

ENVELOPE DETECTOR WATCHDOG DISABLED

RESERVED

ENABLE REG 14 DEMOD PARAMETERS

PROHIBIT CALACTIVE

ENABLE DEMOD DURING CAL

FORCE CALACTIVE

I,Q TO TxRxCLK, TxRxDATA

POWER DOWN DDT AND ED IN T/4 MODE

Tx TEST MODES

Tx CARRIER ONLY

Tx +VE TONE ONLY

Tx –VE TONE ONLY

Tx "1010" PATTERN

Tx PN9 DATA, AT PROGRAMED RATE

Tx SYNC BYTE REPEATEDLY

Σ-Δ TEST MODES

DEFAULT, 3RD ORDER SD, NO DITHER

1ST ORDER SD

2ND ORDER SD

DITHER TO FIRST STAGE

DITHER TO SECOND STAGE

DITHER TO THIRD STAGE

DITHER × 8

DITHER × 32

PLL TEST MODES

NORMAL OPERATION

R DIV

N DIV

RCNTR/2 ON MUXOUT

NCNTR/2 ON MUXOUT

ACNTR TO MUXOUT

PFD PUMP UP TO MUXOUT

PFD PUMP DN TO MUXOUT

SDATA TO MUXOUT (OR SREAD?)

ANALOG LOCK DETECT ON MUXOUT

END OF COARSE CAL ON MUXOUT

END OF FINE CAL ON MUXOUT

TEST MUX SELECTS DATA

LOCK DETECT PERCISION

RESERVED

PFD/CP TEST MODES

DEFAULT, NO BLEED

(+VE) CONSTANT BLEED

(–VE) CONSTANT BLEED

(–VE) PULSED BLEED

(–VE) PULSE BLD, DELAY UP?

CP PUMP UP

CP TRI-STATE

CP PUMP DN

CLK MUXES on CLKOUT pin

CAL OVERRIDE

AUTO CAL

OVERRIDE GAIN

OVERRIDE BW

OVERRIDE BW AND GAIN

FORCE LD HIGH

NORMAL

FORCE

REG1 PD

NORMAL

PWR DWN

SDATA TO CDR

FORCE NEW PRESCALER CONFIG.

FOR ALL N

NORMAL OPERATION

NORMAL, NO OUTPUT

DEMOD CLK

CDR CLK

SEQ CLK

BB OFFSET CLK

SIGMA DELTA CLK

ADC CLK

TxRxCLK

3FSK SLICER ON TxRxDATA

Figure 77. Register 15—Test Mode Register Map

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