CS49400 datasheet(90/100 Pages) CIRRUS

90 / 100 page

Digital-audio frame clock input. FLRCLKN1 typically is run at the sampling frequency.

FLRCLKN1 operates asynchronously from all other DSPAB clocks. The polarity of FLRCLKN1

for a particular subframe can be programmed by the DSP.

BIDIRECTIONAL - Default: INPUT

FSDATAN1 — PCM Audio Data Input One

Digital-audio data input that can accept from one compressed line or 2 channels of PCM data.

FSDATAN1 can be sampled with either edge of FSCLKN1, depending on how FSCLKN1 has

been configured. INPUT

CMPCLK, FSCLKN2 — PCM Audio Input Bit Clock

Digital-audio bit clock input. FSCLKN2 operates asynchronously from all other DSPAB clocks.

Theactiveedgeof FSCLKN2 canbeprogrammedby the DSP.

BIDIRECTIONAL - Default: INPUT

CMPDAT, FSDATAN2 — PCM Audio Data Input Number Two

Digital-audio data input that can accept either one compressed line or 2 channels of PCM

data. FSDATAN2 can be sampled with either edge of FSCLKN2, depending on how FSCLKN2

has been configured.

BIDIRECTIONAL - Default: INPUT

FDBCK — Reserved

This pin is reserved and should be pulled up with an external 3.3k resistor. INPUT

FDBDA — Reserved

This pin is reserved and should be pulled up with an external 3.3k resistor.

BIDIRECTIONAL - Default: INPUT

PLLVDD — PLL Supply Voltage

2.5 V PLL supply.

PLLVSS — PLL Ground Voltage

PLL ground.

RESET — Master Reset Input

Asynchronous active-low master reset input. Reset should be low at power-up to initialize the

DSP and to guarantee that the device is not active during initial power-on stabilization periods.

At the rising edge of reset the host interface mode of DSPAB is selected contingent on the

stateof the FHS0, FHS1, and FHS2 pins. At therisingedgeof reset thehost interface mode

of DSPC is selected contingent on the state of the UHSO, UHS1, and UHS2 pins. If reset is

low all bidirectional pins are high-Z inputs. INPUT

TEST — Reserved

CS49400 bảng dữ liệu(PDF) 90 Page - Cirrus Logic