CS49300 datasheet(8/86 Pages) CIRRUS

8 / 86 page

CS49300 Family DSP

DS339PP4

1.7. Switching Characteristics — Intel® Host Mode

(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =

1/DCLK. The DSP clock can be defined as follows:

External CLKIN Mode:

DCLK == CLKIN/4 before and during boot

DCLK == CLKIN after boot

Internal Clock Mode:

DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns

DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for

characterization to minimize the effects of external bus capacitance.

3. See Tidd from Intel Host Mode in Table 6 on page 43

Parameter

Symbol

Min

Max

Unit

Address setup before CS and RD low or CS and WR low

Tias

Address hold time after CS and RD low or CS and WR low

Tiah

Delay between RD then CS low or CS then RD low

Ticdr

∞

Data valid after CS and RD low

(Note 3)

Tidd

-21

CS and RD low for read

(Note 1)

Tirpw

DCLKP + 10

Data hold time after CS or RD high

Tidhr

Data high-Z after CS or RD high

(Note 2)

Tidis

-22

CS or RD high to CS and RD low for next read

(Note 1)

Tird

2*DCLKP + 10

CS or RD high to CS and WR low for next write

(Note 1)

Tirdtw

2*DCLKP + 10

Delay between WR then CS low or CS then WR low

Ticdw

∞

Data setup before CS or WR high

Tidsu

CS and WR low for write

(Note 1)

Tiwpw

DCLKP + 10

Data hold after CS or WR high

Tidhw

CS or WR high to CS and RD low for next read

(Note 1)

Tiwtrd

2*DCLKP + 10

CS or WR high to CS and WR low for next write

(Note 1)

Tiwd

2*DCLKP + 10

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