LM98714CCMTSLASHNOPB datasheet(5/114 Pages) TI1

5 / 114 page

LM98714

www.ti.com

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

PIN DESCRIPTIONS(1)

Name

I/O

Typ

Res

Description

CLK3

Configurable sensor control output.

CLK2

Configurable sensor control output.

CLK1

Configurable sensor control output.

Sensor - Shift or transfer control signal for CCD and CIS sensors.

RESET

Active-low master reset. NC when function not being used.

SH_R

External request for an SH pulse.

SDIO

I/O

Serial Interface Data Input

SCLK

Serial Interface shift register clock.

SEN

Active-low chip enable for the Serial Interface.

AGND

Analog ground return.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

VREFB

Bottom of ADC reference. Bypass with a 0.1

μF capacitor to ground.

VREFT

Top of ADC reference. Bypass with a 0.1

μF capacitor to ground.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

AGND

Analog ground return.

VCLP

Input Clamp Voltage. Normally bypassed with a 0.1

μF, and a 4.7μF capacitor to AGND.

An external reference voltage may be applied to this pin.

VCLP

Input Clamp Voltage. Normally bypassed with a 0.1

μF , and a 10μF capacitor to AGND.

An external reference voltage may be applied to this pin.

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

AGND

Analog ground return.

OSR

Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.

AGND

Analog ground return.

OSG

Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.

AGND

Analog ground return.

OSB

Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.

AGND

Analog ground return.

DGND

Digital ground return.

Power supply input for internal voltage reference generator. Bypass this supply pin with a

0.1

μF capacitor.

DVB

Digital Core Voltage bypass. Not an input. Bypass with 0.1

μF capacitor to DGND.

INCLK+

Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is

selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.

INCLK-

Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.

DOUT7/

Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.

TXCLK+

DOUT6/

Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.

TXCLK-

DOUT5/

Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.

TXOUT2+

DOUT4/

Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.

TXOUT2-

DOUT3/

Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.

TXOUT1+

DOUT2/

Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.

TXOUT1-

(1)

(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down

with an internal resistor.).

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