TTP-C2NF Communication Controller – Data Sheet

AS8202NF

Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.

21

Ap p e n d i x

Feature Comparison

Feature

C2

AS8202

C2NF

AS8202NF

Conformance with TTP

Specification Version 1.0.

yes

yes

TTP controller

RISC CPU

(PCU)

RISC CPU

(PCU)

Firmware on Chip

yes

(Flash)

Data load phase at power-on

no

(MEDL in Flash)

yes

(MEDL in RAM)

Interface to TTP Physical Layer

- synch.(MII)

- asynch.

- synch.(MII)

TTP Bus data coding

(asynchronous interface)

MFM

MFM

Manchester

IFG (Inter Frame Gap)

45µs

23µs

Interface to Host CPU

16 Bit

16 Bit

Supported Host CPU Bus Type

Intel

Intel

Host CPU access speed

(without “read ahead”)

<250ns

<150ns

(Intel)

Read ahead / Posted write

no

yes (access time

<100ns)

CNI-RAM configuration

fixed

configurable

(4kB to 28kB in 4kB

steps)

MEDL check method

one CRC

(firmware)

„block“ CRC

(firmware)

Instruction RAM (I-RAM) check

Method

once

(firmware)

Parity Bit

(+firmware)

Support for X-Frames

yes

yes

Baudrate on TTP Bus

asynchronous mode

synchronous mode

up to 5MBd

25MBd

up to 5MBd

up to 25MBd

Process

0,35µ

CMOS+Flash

0,35µ

CMOS

SRAM

12kByte

40kByte

ROM

8kByte

Flash

32kByte

-

Power supply

3,3V

3,3V

Temperature range (°C)

0 to +70

-40 to +125

Package

LQFP80

LQFP80

Note 1: The chip is designed to allow inclusion of a stable protocol code (or customized protocol code) into the ROM by changing the ROM mask in the

production process. This would eliminate the need of loading the protocol firmware code into the instruction code RAM.