TTP-C2NF Communication Controller – Data Sheet

AS8202NF

Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.

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Synchronous READYB Generation

Synchronous READYB is aligned to host clock (with pulse duration of one host clock cycle) to

fulfill the required host timing constraints for input setup and input hold time to/after host clock

rising edge.

Note:

Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of operation. Due to possible

metastability occurrence, it is not recommended to be used in safety critical systems.

8.2.

Reset and Oscillator

Pin Name

Mode

Comment

XIN0

analog

main oscillator input (external clock input)

XOUT0

analog

main oscillator output

XIN1

analog

bus guardian oscillator input (external clock input)

XOUT1

analog

bus guardian oscillator output

PLLOFF

in

PLL disable

RESETB

in

external reset

External Reset Signal

To issue a reset of the chip the RESETB port has to be driven low for at least 1 us. Pulses

under 50 ns duration are discarded. At power-up the reset must overlap the build-up time of the

power supply.

Integrated Power-On Reset

The Device has an internal Power-On Reset generator. When supply voltage ramps up, the

internal reset signal is kept active (low) for 33 µs typical.

Parameter

Symbol

Min

Typ

Max

Unit

supply voltage slope

dV/dt

551

-

-

V/ms

power on reset active time after VDD > 1,0V

tpores

25

33

49

µs

Note 1: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid and oscillator inputs active.

Oscillator Circuitry

The internal oscillators for main and bus guardian clock require external quartzes or external

oscillators. The main clock features a PLL multiplying a 10 MHz XIN0/XOUT0 oscillation to an

internal frequency of 40 MHz when enabled.

asynchronous READYB

RAM_CLK_TESTSE

synchronous READYB

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