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MPC8347VRAGDB bảng dữ liệu(PDF) 16 Page - Freescale Semiconductor, Inc |
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MPC8347VRAGDB bảng dữ liệu(HTML) 16 Page - Freescale Semiconductor, Inc |
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16 / 99 page ![]() MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 16 Freescale Semiconductor DDR and DDR2 SDRAM Table 11 lists the PLL and DLL lock times. 6 DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8347EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR and DRR2 SDRAM. NOTE The information in this document is accurate for revision 3.0 silicon and later. For information on revision 1.1 silicon and earlier versions see the MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications. See Section 22.1, “Part Numbers Fully Addressed by This Document,” for silicon revision level determination. 6.1 DDR and DDR2 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8347EA when GVDD(typ) = 1.8 V. Table 11. PLL and DLL Lock Times Parameter/Condition Min Max Unit Notes PLL lock times — 100 μs— DLL lock times 7680 122,880 csb_clk cycles 1, 2 Notes: 1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.” Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter/Condition Symbol Min Max Unit Notes I/O supply voltage GVDD 1.71 1.89 V 1 I/O reference voltage MVREF 0.49 × GV DD 0.51 × GV DD V2 I/O termination voltage VTT MVREF –0.04 MVREF +0.04 V 3 Input high voltage VIH MVREF + 0.125 GVDD +0.3 V — Input low voltage VIL –0.3 MVREF –0.125 V — Output leakage current IOZ –9.9 9.9 μA4 Output high current (VOUT = 1.420 V) IOH –13.4 — mA — |
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