MPC8347VRAGDB datasheet(29/99 Pages) FREESCALE

29 / 99 page

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.2.3.1

TBI Transmit AC Timing Specifications

Table 29 provides the TBI transmit AC timing specifications.

Figure 14 shows the TBI transmit AC timing diagram.

Figure 14. TBI Transmit AC Timing Diagram

8.2.3.2

TBI Receive AC Timing Specifications

Table 30 provides the TBI receive AC timing specifications.

Table 29. TBI Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

GTX_CLK clock period

tTTX

—8.0

—

GTX_CLK duty cycle

tTTXH/tTTX

—

GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay

tTTKHDX

1.0

—

5.0

GTX_CLK clock rise (20%–80%)

tTTXR

——

1.0

GTX_CLK clock fall time (80%–20%)

tTTXF

——

1.0

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit

timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V)

or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until

the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on

three letters representing the clock of a particular function. For example, the subscript of tTTX represents the TBI (T) transmit

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 30. TBI Receive AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

PMA_RX_CLK clock period

tTRX

16.0

PMA_RX_CLK skew

tSKTRX

7.5

—

8.5

RX_CLK duty cycle

tTRXH/tTRX

—

GTX_CLK

TXD[7:0]

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDX

TX_EN

TX_ER

MPC8347VRAGDB bảng dữ liệu(PDF) 29 Page - Freescale Semiconductor, Inc

MPC8347VRAGDB bảng dữ liệu(HTML) 29 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

bảng dữ liệu tải về

Link URL