MPC8347VRAGDB datasheet(13/99 Pages) FREESCALE

13 / 99 page

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the device.

4.1

DC Electrical Characteristics

Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347EA.

4.2

AC Electrical Characteristics

The primary clock source for the MPC8347EA can be one of two inputs, CLKIN or PCI_CLK, depending

on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the device.

Table 6. CLKIN DC Timing Specifications

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

CLKIN input current

0 V

≤ V

IN ≤ OVDD

IIN

—

±10

μA

PCI_SYNC_IN input current

0 V

≤ V

IN ≤ 0.5 V or

OVDD –0.5 V ≤ VIN ≤ OVDD

IIN

—

±10

μA

PCI_SYNC_IN input current

0.5 V

≤V

IN ≤ OVDD – 0.5 V

IIN

—

±50

μA

Table 7. CLKIN AC

Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

CLKIN/PCI_CLK frequency

fCLKIN

——

MHz

1, 6

CLKIN/PCI_CLK cycle time

tCLKIN

—

CLKIN/PCI_CLK rise and fall time

tKH, tKL

0.6

1.0

2.3

CLKIN/PCI_CLK duty cycle

tKHK/tCLKIN

—

CLKIN/PCI_CLK jitter

—

±150

4, 5

Notes:

1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless

of input frequency.

MPC8347VRAGDB bảng dữ liệu(PDF) 13 Page - Freescale Semiconductor, Inc

MPC8347VRAGDB bảng dữ liệu(HTML) 13 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

bảng dữ liệu tải về

Link URL