TAS5342DDVRG4 datasheet(23/29 Pages) TI

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Overtemperature Protection

DEVICE RESET

Undervoltage Protection (UVP) and Power-On

TAS5342

SLAS557B–SEPTEMBER 2007–REVISED OCTOBER 2007

PPSC detection is enabled in BTL and PBTL output

VDD or GVDD_X pin results in all half-bridge outputs

configurations, the detection is not performed in SE

immediately being set in the high-impedance (Hi-Z)

mode. To make sure not to trip the PPSC detection

state and SD being asserted low. The device

system it is recommended not to insert resistive load

automatically resumes operation when all supply

to GND_X or PVDD_X.

voltages have increased above the UVP threshold.

The TAS5342 has a two-level temperature-protection

Two reset pins are provided for independent control

system that asserts an active-low warning signal

of half-bridges A/B and C/D. When RESET_AB is

(OTW) when the device junction temperature

asserted low, all four power-stage FETs in half--

exceeds 125°C (nominal) and, if the device junction

bridges A and B are forced into a high-impedance

temperature exceeds 155°C (nominal), the device is

(Hi-Z) state. Likewise, asserting RESET_CD low

put into thermal shutdown, resulting in all half-bridge

forces all four power-stage FETs in half-bridges C

outputs being set in the high-impedance (Hi-Z) state

and D into a high-impedance state. Thus, both reset

and SD being asserted low. OTE is latched in this

pins are well suited for hard-muting the power stage if

case. To clear the OTE latch, either RESET_AB or

needed.

RESET_CD must be asserted. Thereafter, the device

In BTL modes, to accommodate bootstrap charging

resumes normal operation.

prior to switching start, asserting the reset inputs low

enables weak pulldown of the half-bridge outputs. In

the SE mode, the weak pulldowns are not enabled,

Reset (POR)

and it is therefore recommended to ensure bootstrap

The UVP and POR circuits of the TAS5342 fully

capacitor charging by providing a low pulse on the

protect the device in any power-up/down and

PWM inputs when reset is asserted high.

brownout situation. While powering up, the POR

Asserting either reset input low removes any fault

circuit resets the overload circuit (OLP) and ensures

information to be signalled on the SD output, i.e., SD

that all circuits are fully operational when the

is forced high.

GVDD_X and VDD supply voltages reach stated in

the Electrical Characteristics Table. Although

A rising-edge transition on either reset input allows

GVDD_X and VDD are independently monitored, a

the device to resume operation after an overload

supply voltage drop below the UVP threshold on any

fault. To ensure thermal reliability, the rising edge of

reset must occur no sooner than 4ms after the falling

edge of SD.

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