TAS5342DDVRG4 datasheet(20/29 Pages) TI

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THEORY OF OPERATION

POWER SUPPLIES

SYSTEM POWER-UP/POWER-DOWN

Powering Up

Powering Down

TAS5342

SLAS557B–SEPTEMBER 2007–REVISED OCTOBER 2007

Special attention should be paid to the power-stage

power supply; this includes component selection,

PCB placement, and routing. As indicated, each

To facilitate system design, the TAS5342 needs only

half-bridge has independent power-stage supply pins

a 12-V supply in addition to the (typical) 31.5-V

(PVDD_X). For optimal electrical performance, EMI

power-stage supply. An internal voltage regulator

compliance, and system reliability, it is important that

provides suitable voltage levels for the digital and

each PVDD_X pin is decoupled with a 100-nF

low-voltage analog circuitry. Additionally, all circuitry

ceramic capacitor placed as close as possible to

requiring a floating voltage supply, e.g., the high-side

each supply pin. It is recommended to follow the PCB

gate drive, is accommodated by built-in bootstrap

layout of the TAS5342 reference design. For

circuitry requiring only an external capacitor for each

additional information on recommended power supply

half-bridge.

and required components, see the application

In order to provide outstanding electrical and

diagrams given previously in this data sheet.

acoustical characteristics, the PWM signal path

The 12-V supply should be from a low-noise,

including gate drive and output stage is designed as

low-output-impedance voltage regulator. Likewise, the

identical, independent half-bridges. For this reason,

31.5-V power-stage supply is assumed to have low

each half-bridge has separate gate drive supply

output impedance and low noise. The power-supply

(GVDD_X), bootstrap pins (BST_X), and power-stage

sequence is not critical as facilitated by the internal

supply pins (PVDD_X). Furthermore, an additional pin

power-on-reset circuit. Moreover, the TAS5342 is fully

(VDD) is provided as supply for all common circuits.

protected against erroneous power-stage turnon due

Although supplied from the same 12-V source, it is

to parasitic gate charging. Thus, voltage-supply ramp

highly

recommended

separate

GVDD_A,

rates (dV/dt) are non-critical within the specified

GVDD_B, GVDD_C, GVDD_D, and VDD on the

range (see the Recommended Operating Conditions

printed-circuit board (PCB) by RC filters (see

section of this data sheet).

application diagram for details). These RC filters

provide the recommended high-frequency isolation.

Special attention should be paid to placing all

decoupling capacitors as close to their associated

SEQUENCE

pins as possible. In general, inductance between the

power supply pins and decoupling capacitors must be

avoided. (See reference board documentation for

The TAS5342 does not require a power-up sequence.

additional information.)

The outputs of the H-bridges remain in a high-imped-

For a properly functioning bootstrap circuit, a small

ance state until the gate-drive supply voltage

ceramic capacitor must be connected from each

(GVDD_X) and VDD voltage are above the

bootstrap pin (BST_X) to the power-stage output pin

undervoltage protection (UVP) voltage threshold (see

(OUT_X). When the power-stage output is low, the

the Electrical Characteristics section of this data

bootstrap capacitor is charged through an internal

sheet). Although not specifically required, it is

diode connected between the gate-drive power--

recommended to hold RESET_AB and RESET_CD in

supply pin (GVDD_X) and the bootstrap pin. When

a low state while powering up the device. This allows

the power-stage output is high, the bootstrap

an internal circuit to charge the external bootstrap

capacitor potential is shifted above the output

capacitors by enabling a weak pulldown of the

potential and thus provides a suitable voltage supply

half-bridge output.

for the high-side gate driver. In an application with

When the TAS5342 is being used with TI PWM

PWM switching frequencies in the range from 352

modulators such as the TAS5518, no special

kHz to 384 kHz, it is recommended to use 33-nF

attention to the state of RESET_AB and RESET_CD

ceramic capacitors, size 0603 or 0805, for the

is required, provided that the chipset is configured as

bootstrap supply. These 33-nF capacitors ensure

recommended.

sufficient energy storage, even during minimal PWM

duty cycles, to keep the high-side power stage FET

(LDMOS) fully turned on during the remaining part of

the PWM cycle. In an application running at a

The TAS5342 does not require a power-down

reduced switching frequency, generally 192 kHz, the

sequence. The device remains fully operational as

bootstrap capacitor might need to be increased in

long as the gate-drive supply (GVDD_X) voltage and

value.

VDD voltage are above the undervoltage protection

(UVP) voltage threshold (see the Electrical

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