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STM8S005C6T6C bảng dữ liệu(PDF) 92 Page - STMicroelectronics |
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STM8S005C6T6C bảng dữ liệu(HTML) 92 Page - STMicroelectronics |
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92 / 103 page ![]() Table 48: ESD absolute maximum ratings Unit Maximum value (1) Class Conditions Ratings Symbol V 2000 A TA = +25°C, conforming to JESD22-A114 Electrostatic discharge voltage (Human body model) VESD(HBM) V 1000 IV TA=+25°C, conforming to JESD22-C101 Electrostatic discharge voltage (Charge device model) VESD(CDM) (1) Data based on characterization results, not tested in production Static latch-up 9.3.12.6 Two complementary static tests are required on 10 parts to assess the latch-up performance: • A supply overvoltage (applied to each power supply pin) • A current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 49: Electrical sensitivities Class (1) Conditions Parameter Symbol A TA = +25 °C Static latch-up class LU A TA = +85 °C (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). DocID022186 Rev 3 92/103 STM8S005K6 STM8S005C6 Electrical characteristics |
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