JS28F640P33TF70 datasheet(42/88 Pages) NUMONYX

42 / 88 page

P33-65nm

Datasheet

Jul 2011

Order Number: 208034-04

The device programs the 64-bit and 128-bit user-programmable OTP Register data 16

bits at a time (see Figure 36, “OTP Register Programming Flowchart” on page 79).

Issuing the Program OTP Register command outside of the OTP Register’s address

space causes a program error (SR.4 set). Attempting to program a locked OTP Register

causes a program error (SR.4 set) and a lock error (SR.1 set).

Note:

When programming the OTP bits in the OTP Registers for a Top Parameter Device, the

following upper address bits must also be driven properly: A[Max:17] driven high (VIH).

11.2.3

Locking the OTP Registers

Each OTP Register can be locked by programming its respective lock bit in the Lock

issuing the Program Lock Register command, followed by the desired Lock Register

data (see Section 6.2, “Device Command Bus Cycles” on page 18). The physical

addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These

addresses are used when programming the Lock Registers (see Table 7, “Device

Identifier Information” on page 21).

Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the

“factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit OTP

region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all

other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each of

the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP

Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit OTP

Caution:

After being locked, the OTP Registers cannot be unlocked.

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