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STM32F101ZC bảng dữ liệu(PDF) 93 Page - STMicroelectronics

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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Doc ID 14610 Rev 8
93/112
Equation 1: RAIN max formula:
Table 55.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input
pin
160(1)
1.
Based on characterization, not tested in production.
220(1)
µA
fADC
ADC clock frequency
0.6
14
MHz
fS
(2)
2.
Guaranteed by design, not tested in production.
Sampling rate
0.05
1
MHz
fTRIG
(2)
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(3)
3.
VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 3: Pinouts and pin descriptions for further details.
0 (VSSA or VREF-
tied to ground)
VREF+
V
RAIN
(2)
External input impedance
See Equation
1 and Table 56
for details
50
k
Ω
RADC
(2)
Sampling switch resistance
1
k
Ω
CADC
(2)
Internal sample and hold
capacitor
8pF
tCAL
(2)
Calibration time
fADC = 14 MHz
5.9
µs
83
1/fADC
tlat
(2)
Injection trigger conversion
latency
fADC = 14 MHz
0.214
µs
3(4)
4.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 55.
1/fADC
tlatr
(2)
Regular trigger conversion
latency
fADC = 14 MHz
0.143
µs
2(4)
1/fADC
tS
(2)
Sampling time
fADC = 14 MHz
0.107
17.1
µs
1.5
239.5
1/fADC
tSTAB
(2)
Power-up time
0
0
1
µs
tCONV
(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
1
18
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
R
AIN
T
S
f
ADC
C
ADC
2
N2
+
()
ln
×
×
--------------------------------------------------------------
R
ADC
–
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