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STM32F101ZC bảng dữ liệu(PDF) 89 Page - STMicroelectronics |
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STM32F101ZC bảng dữ liệu(HTML) 89 Page - STMicroelectronics |
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89 / 112 page ![]() STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Doc ID 14610 Rev 8 89/112 SPI interface characteristics Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 53. STM32F10xxx SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 10 MHz Slave mode 10 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 8 ns tsu(NSS) (1) 1. Based on characterization, not tested in production. NSS setup time Slave mode 4tPCLK th(NSS) (1) NSS hold time Slave mode 73 tw(SCKH) (1) tw(SCKL) (1) SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 tsu(MI) (1) tsu(SI) (1) Data input setup time Master mode - SPI1 3 Master mode - SPI2 5 Slave mode 4 th(MI) (1) Data input hold time Master mode - SPI1 4 Master mode - SPI2 6 th(SI) (1) Slave mode 5 ta(SO) (1)(2) 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Data output access time Slave mode, fPCLK = 36 MHz, presc = 4 055 Slave mode, fPCLK = 20 MHz 4tPCLK tdis(SO) (1)(3) 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Data output disable time Slave mode 10 tv(SO) (1) Data output valid time Slave mode (after enable edge) 25 tv(MO) (1) Data output valid time Master mode (after enable edge) 6 th(SO) (1) Data output hold time Slave mode (after enable edge) 25 th(MO) (1) Master mode (after enable edge) 6 |
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