ADS5522IPAP datasheet(26/32 Pages) TI

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OUTPUT INFORMATION

ADS5522

SBAS320C – MAY 2004 – REVISED FEBRUARY 2007

The output circuitry of the ADS5522, by design,

minimizes the noise produced by the data switching

The ADC provides 12 data outputs (D11 to D0, with

transients, and, in particular, its coupling to the ADC

D11 being the MSB and D0 the LSB), a data-ready

analog circuitry. Output D2 (pin 51) senses the load

signal (CLKOUT, pin 43), and an out-of-range

capacitance and adjusts the drive capability of all the

indicator (OVR, pin 64) that equals 1 when the

output pins of the ADC to maintain the same output

output reaches the full-scale limits.

slew rate described in the timing diagram of Figure 1.

Care should be taken to ensure that all output lines

Two different output formats (straight offset binary or

(including CLKOUT) have nearly the same load as

two's complement) and two different output clock

D2 (pin 51). This circuit also reduces the sensitivity

polarities (latching output data on rising or falling

of the output timing versus supply voltage or

edge of the output clock) can be selected by setting

temperature. Placing external resistors in series with

DFS (pin 40) to one of four different voltages.

the outputs is not recommended.

Table 3 details the four modes. In addition, output

enable control (OE, pin 41, active high) is provided to

The timing characteristics of the digital outputs

put the outputs into a high-impedance state.

change for sampling rates below the 80 MSPS

maximum sampling frequency. Table 5 and Table 6

In the event of an input voltage overdrive, the digital

show the values of various timing parameters at

outputs go to the appropriate full-scale level. For a

lower sampling frequencies.

positive overdrive, the output code is 0xFFF in

straight offset binary output format and 0x7FF in

To use the input clock as the data capture clock, it is

two's complement output format. For a negative input

necessary to delay the input clock by a delay, td, that

overdrive, the output code is 0x000 in straight offset

results in the desired setup or hold time. Use either

binary output format and 0x800 in two's complement

of the following equations to calculate the value of td.

output format. These outputs to an overdrive signal

Desired setup time = td – tSTART

are ensured through design and characterization.

Desired hold time = tEND – td

Table 5. Timing Characteristics at Additional Sampling Frequencies

tsu (ns)

th (ns)

tSTART (ns)

tEND (ns)

tr (ns)

tf (ns)

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

4.7

6.0

2.1

3.1

2.4

4.2

8.3

12.0

6.6

7.2

5.5

6.4

8.5

2.8

3.5

-1

1.5

8.9

14.5

7.5

7.3

7.8

25.7

2.5

4.7

-9.8

9.5

21.6

7.5

7.6

6.5

-30

-3

11.5

284

370

185

320

515

576

150

Table 6. Timing Characteristics at Additional Sampling Frequencies

CLKOUT, Rise Time

CLKOUT, Fall Time

CLKOUT Jitter, Peak-to-Peak

Input-to-Output Clock Delay

tr (ns)

tf (ns)

tJIT (ps)

tPDI (ns)

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

3.1

3.5

2.6

2.9

260

380

7.8

8.5

9.4

4.8

5.3

4.4

445

650

9.5

10.4

11.4

8.3

9.5

7.6

8.2

800

1200

15.5

20.7

25.5

2610

4400

537

551

567

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