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RESET TIMING CHARACTERISTICS

RESET (Pin 35)

SEN Active

Power Supply

SERIAL PROGRAMMING INTERFACE CHARACTERISTICS

ADS5522

SBAS320C – MAY 2004 – REVISED FEBRUARY 2007

TIMING CHARACTERISTICS (continued)

Typical values given at T

AV

unless otherwise noted

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Time to valid data after coming out of software

1000

power down

Clock

Wakeup time

cycles

Time to valid data after stopping and restarting the

1000

clock

Latency

Time for a sample to propagate to the ADC outputs

17.5

Clock

cycles

Typical values given at T

DRV

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Power-on delay

10

ms

Reset pulse width

Pulse width of active RESET signal

2

µs

Register write delay

Delay from RESET disable to SEN active

2

µs

Power-up time

40

ms

Figure 2. Reset Timing Diagram

The ADS5522 has a three-wire serial interface. The device latches serial data SDATA on the falling edge of

serial clock SCLK when SEN is active.

• Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.

• Minimum width of data stream for a valid loading is 16 clocks.

• Data is loaded at every 16th SCLK falling edge while SEN is low.

• In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.

• Data can be loaded in multiples of 16-bit words within a single active SEN pulse.

• The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.

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