AM79C970A datasheet(127/219 Pages) AMD

127 / 219 page

P R E L I M I N A R Y

AMD

127

Am79C970A

15–0 CRBAU

Contains the upper 16 bits of the

current receive buffer address at

which the PCnet-PCI II controller

will store incoming frame data.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR20: Current Transmit Buffer Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

CXBAL

Contains the lower 16 bits of the

current transmit buffer address

from which the PCnet-PCI II con-

troller is transmitting.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR21: Current Transmit Buffer Address Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 CXBAU

Contains the upper 16 bits of the

current transmit buffer address

from which the PCnet-PCI II con-

troller is transmitting.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR22: Next Receive Buffer Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

NRBAL

Contains the lower 16 bits of the

next receive buffer address to

which the PCnet-PCI II controller

will store incoming frame data.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR23: Next Receive Buffer Address Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NRBAU

Contains the upper 16 bits of the

next receive buffer address to

which the PCnet-PCI II controller

will store incoming frame data.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR24: Base Address of Receive Descriptor

Ring Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

BADRL

Contains the lower 16 bits of the

base address of the receive

descriptor ring.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR25: Base Address of Receive Descriptor

Ring Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 BADRU

Contains the upper 16 bits of the

base address of the receive

descriptor ring.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

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