AM79C970A datasheet(68/219 Pages) AMD

68 / 219 page

AMD

P R E L I M I N A R Y

Am79C970A

controller, then the software must not read ahead to the

next descriptor. The software should wait at a descriptor

it does not own until the PCnet-PCI II controller sets

OWN to ZERO to release ownership to the software.

(When LAPPEN (CSR3, bit 5) is set to ONE, this rule is

modified. See the LAPPEN description.)

At initialization, the PCnet-PCI II controller reads the

base address of both the transmit and receive descriptor

rings into CSRs for use by the PCnet-PCI II controller

during subsequent operations.

The following figure illustrates the relationship between

the initialization base address, the initialization block,

the receive and transmit descriptor ring base ad-

dresses, the receive and transmit descriptors and the

receive and transmit data buffers, when SSIZE32 is

cleared to ZERO.

Note that the value of CSR2, bits 15–8 is used as the

upper 8-bits for all memory addresses during bus

master transfers.

19436A-35

Initialization

Block

IADR[15:0]

IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLE

RES

RDRA[23:16]

TLE

RES

TDRA[23:16]

Rcv

Buffers

RMD0

RMD

Rcv Descriptor

Ring

•

1st desc.

start

2nd

desc.

RMD0

Xmt

Buffers

TMD

Xmt Descriptor

Ring

•

1st desc.

start

2nd

desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Figure 32. 16-Bit Software Model

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