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ZSSC3036CC1C bảng dữ liệu(PDF) 33 Page - List of Unclassifed Manufacturers |
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ZSSC3036CC1C bảng dữ liệu(HTML) 33 Page - List of Unclassifed Manufacturers |
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33 / 49 page ![]() ZSSC3036 Low-Power 16-Bit Sensor Signal Conditioner IC Data Sheet May 28, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 33 of 49 3.6.3. Memory Contents Table 3.8 MTP Memory Content Assignments MTP Address Word / Bit Range Default Setting Description Notes / Explanations 00HEX 15:0 0000HEX Cust_ID0 Customer ID byte 0 (combines with memory word 01HEX to form customer ID) 01HEX 15:0 0000HEX Cust_ID1 Customer ID byte 1 (combines with memory word 00HEX to form customer ID) Interface Configuration 02HEX 6:0 000 0000BIN Slave_Addr I²C ™ slave address; valid range: 00HEX to 7FHEX (default: 00HEX), Remark: address codes 04HEX to 07HEX are reserved for entering the I 2C™ High Speed Mode 8:7 00BIN - Reserved 9 0BIN SS_polarity Determines the polarity of the Slave Select pin (SS) for SPI operation: 0 Slave Select is active low (SPI and ZSSC3036 are active if SS==0) 1 Slave Select is active high (SPI and ZSSC3036 are active if SS==1) 11:10 00BIN CKP_CKE Clock polarity and clock-edge select —determines polarity and phase of SPI interface clock with the following modes: 00 SCLK is low in idle state, data latch with rising edge and data output with falling edge 01 SCLK is low in idle state, data latch with falling edge and data output with rising edge 10 SCLK is high in idle state, data latch with falling edge and data output with rising edge 11 SCLK is high in idle state, data latch with rising edge and data output with falling edge 15:12 - Not assigned |
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