PIC10LF322T-EMCSQTP datasheet(134/210 Pages) MICROCHIP

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PIC10(L)F320/322

DS41585A-page 134

Preliminary

 2011 Microchip Technology Inc.

20.5

Interrupts

When the Accumulator overflows, the NCOx Interrupt

Flag bit, NCOxIF, of the PIR1 register is set. To enable

this interrupt event, the following bits must be set:

• NxEN bit of the NCOxCON register

• NCOxIE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt must be cleared by software by clearing

the NCOxIF bit in the Interrupt Service Routine.

20.6

Effects of a Reset

All of the NCOx registers are cleared to zero as the

result of a Reset.

20.7

Operation In Sleep

The NCO module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock source selected remains active.

The HFINTOSC remains active during Sleep when the

NCO module is enabled and the HFINTOSC is

selected as the clock source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the NCO clock

source, when the NCO is enabled, the CPU will go idle

during Sleep, but the NCO will continue to operate and

the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

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