PIC10LF322T-EMCSQTP datasheet(42/210 Pages) MICROCHIP

42 / 210 page

PIC10(L)F320/322

DS41585A-page 42

Preliminary

 2011 Microchip Technology Inc.

6.1

Operation

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

events)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1 register)

The INTCON and PIR1 registers record individual inter-

rupts via interrupt flag bits. Interrupt flag bits will be set,

regardless of the status of the GIE, PEIE and individual

interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

6.2

Interrupt Latency

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is 3 or 4 instruction cycles. For asynchronous

interrupts, the latency is 3 to 5 instruction cycles,

depending on when the interrupt occurs. See Figure 6-2

and Section 6.3 “Interrupts During Sleep” for more

details.

Note 1:

Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

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