TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003

6

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

functional description

The TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each.

and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with the

rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)

corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising

edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown

in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.

LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears with

the rising edge of CLK5.

VI(1)

VI(2)

VI(3)

VI(4)

CLK1

CLK2

CLK3

CLK4

S(1)

C(1)

S(2)

C(2)

S(3)

C(3)

S(4)

C(4)

S(1)

H(1)

C(1)

S(3)

H(3)

C(3)

H(0)

C(0)

S(2)

H(2)

C(2)

S(4)

H(4)

LD(– 2)

OUT(– 2)

OUT(–1)

OUT(0)

OUT(1)

ANALOG IN

(sampling points)

CLK (clock)

Upper Comparators Block

Upper Data

Lower Reference Voltage

Lower Comparators Block (A)

Lower Data (A)

Lower Comparators Block (B)

Lower Data (B)

D1 – D8 (data output)

UD(0)

RV(0)

UD(1)

RV(1)

UD(2)

RV(2)

UD(3)

RV(3)

LD(– 1)

LD(0)

LD(1)

LD(2)

CLK5

Figure 2. Internal Functional Timing Diagram