ADS5520IPAPR datasheet(10/38 Pages) TI1

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DFS t

DD t VDFS t

DFS u

ADS5520

SBAS310F – MAY 2004 – REVISED OCTOBER 2008....................................................................................................................................................... www.ti.com

Table 3. Serial Register Table(1)

D11

D10

DESCRIPTION

DLL

Clock DLL

CTRL

Internal DLL is on; recommended for 60 MSPS to 125 MSPS

clock speeds.

Internal DLL is off; recommended for 2 MSPS to 80 MSPS

clock speeds.

TP<1>

TP<0>

Test Mode

Normal mode of operation

All outputs forced to 0

All outputs forced to 1

Each output bit toggles between 0 and 1. (2)(3)

PDN

Power Down

Normal mode of operation

Device is put in power-down (low-current) mode.

(1)

The register contents default to the appropriate setting for normal operation up on RESET.

(2)

The patterns given are applicable to the straight offset binary output format. If 2's complement output format is selected, the test mode

outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.

(3)

While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. For

example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.

Table 4. Data Format Select (DFS) Table

DFS-PIN VOLTAGE (VDFS)

DATA FORMAT

CLOCK OUTPUT POLARITY

Straight Binary

Data valid on rising edge

2's complement

Data valid on rising edge

Straight Binary

Data valid on falling edge

2's complement

Data valid on falling edge

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