PCF8536AT datasheet(49/74 Pages) NXP

49 / 74 page

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

49 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

9.2.7 I2C-bus slave address

Device selection depends on the I2C-bus slave address. Two different I2C-bus slave

addresses can be used to address the PCF8536 (see Table 37).

The least significant bit of the slave address byte is bit R/W. Bit 1 of the slave address is

defined by connecting the input A0 to either VSS (logic 0) or VDD (logic 1). Therefore, two

instances of PCF8536 can be distinguished on the same I2C-bus.

9.2.8 I2C-bus protocol

The I2C-bus protocol is shown in Figure 36. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two PCF8536 slave

addresses available. All PCF8536 with the corresponding A0 level acknowledge in

parallel to the slave address, but any PCF8536 with the alternative A0 level ignore the

whole I2C-bus transfer.

After acknowledgement, a control byte follows (see Section 9.1 on page 46).

The display bytes are stored in the display RAM at the address specified by the RAM data

pointer and PWM data is stored at the address pointed to by the PWM data pointer.

The acknowledgement after each byte is made only by the addressed PCF8536. After the

last data byte, the I2C-bus master issues a STOP condition (P). Alternatively a START

may be issued to RESTART an I2C-bus access.

Table 37.

I2C slave address

Slave address

Bit

MSB

LSB

011

100

R/W

Fig 36. I2C-bus protocol write mode

EXAMPLES

a) transmit two byte of RAM data

013aaa462

S 0 1110

control byte

slave address

RAM/command byte

RAM DATA

R/W = 0

S 0 1110

b) transmit two command bytes

COMMAND

S 0 1110

1 0

COMMAND

c) transmit one command byte and two RAM date bytes

COMMAND

S 0 1110

1 0

RAM DATA

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