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LNBH26 bảng dữ liệu(PDF) 23 Page - STMicroelectronics |
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LNBH26 bảng dữ liệu(HTML) 23 Page - STMicroelectronics |
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23 / 38 page ![]() LNBH26 I²C interface protocol Doc ID 022771 Rev 1 23/38 N/A = Reserved bit. All bits reset to 0 at power-on. Table 8. DATA 2 (Read/Write register. Register address = 0X3) Bit Name CH Value Description Bit 0 (LSB) TEN-A A 1 22 kHz tone enabled. Tone output controlled by the DSQIN pin 0 22 kHz tone output disabled Bit 1 LPM-A 1 Low power mode activated (used only with 22 kHz tone output disabled) 0 Low power mode deactivated (keep always LPM=0 during 22 kHz tone transmission) Bit 2 EXTM-A 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal Bit 3 N/A 0 Reserved. Keep to “0” Bit 4 TEN-B B 1 22 kHz tone enabled. Tone output controlled by the DSQIN pin 0 22 kHz tone output disabled Bit 5 LPM-B 1 Low power mode activated (used only with 22 kHz tone output disabled) 0 Low power mode deactivated (keep always LPM=0 during 22 kHz tone transmission) Bit 6 EXTM-B 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal Bit 7 (MSB) N/A 0 Reserved. Keep to “0” |
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