07XSC200 datasheet(40/51 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

07XSC200

Figure 15. Overcurrent Profile with OCHI bit set to ‘1’

The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17.

Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 18.

Address 00101—GLObal configuration regIster (GCR)

The GCR register allows the MCU to configure the device through the SPI.

Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs

HS[0:1] with PWMR register device in Fail-safe mode in case of VDD < VDD(FAIL).

Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:1]

with PWMR register (the direct input states are ignored).

Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 19.

Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 20.

Table 17. Output Steady State Selection

OCLO1 (D2) OCLO0 (D1)

Steady State Current

OCLO2 (default)

OCLO3

OCLO4

OCLO1

Table 18. Overcurrent Mode Selection

OC_mode_s (D0)

Overcurrent Mode

only inrush current management (default)

inrush current and bulb cooling

management

Table 19. PWM Module Selection

PWM_en (D7) CLOCK_sel (D6)

PWM module

PWM module disabled (default)

PWM module enabled with external

clock from CLOCK

PWM module enabled with

internal calibrated clock

IOCH1

IOCH2

IOC1

IOC2

IOC3

IOC4

IOCL3

IOCL2

IOCL1

tOC1

tOC2

tOC3 tOC4 tOC5 tOC6

tOC7

Time

IOCL4

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