AD9266-80EBZ datasheet(23/32 Pages) AD

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Data Sheet

AD9266

Rev. A | Page 23 of 32

TIMING

The AD9266 provides latched data with a pipeline delay of

eight clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9266. These

transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9266 is 3 MSPS. At

clock rates below 3 MSPS, dynamic performance may degrade.

Data Clock Output (DCO)

The AD9266 provides a data clock output (DCO) signal that is

intended for capturing the data in an external register. The CMOS

data outputs are valid on the rising edge of DCO, unless the DCO

clock polarity has been changed via the SPI. See Figure 2 for

a graphical timing description.

Table 12. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

< −VREF − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= −VREF

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= 0

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

1111 1111 1111 1111

0111 1111 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

1111 1111 1111 1111

0111 1111 1111 1111

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