TMS320DM6467CCUT datasheet(93/355 Pages) TI

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TMS320DM6467

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SPRS403H – DECEMBER 2007 – REVISED JUNE 2012

4.3.2.3

Video and TSIF Clock Disable

The Video Source Clock Disable (VSCLKDIS) register allows the user to disable the selected Video

(VPIF), TSIF, and CRGEN module input clocks.

Note: To ensure glitch-free operation, the clock should be disabled before changing the clock source

frequency or muxing via the VIDCLKCTL and TSIFCTL.

RESERVED

R-0000 0000 0000 0000

RESERVED

VID3

VID2

VID1

VID0

TSIFCNT1 TSIFCNT0 TSIFTX1

TSIFTX0

TSIFRX1

TSIFRX0

CRG1

CRG0

R-0000

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 4-4. VSCLKDIS Register [0x01C4 006C]

Table 4-6. VSCLKDIS Register Bit Descriptions

BIT

NAME

DESCRIPTION

31:12

RESERVED

Reserved. Read returns "0".

VPIF Channel 3 Clock Disable.

VID3

0 = Clock enabled.

1 = Clock disabled.

VPIF Channel 2 Clock Disable.

VID2

0 = Clock enabled.

1 = Clock disabled.

VPIF Channel 1 Clock Disable.

VID1

0 = Clock enabled.

1 = Clock disabled.

VPIF Channel 0 Clock Disable.

VID0

0 = Clock enabled.

1 = Clock disabled.

TSIF1 Counter Clock Disable.

TSIFCNT1

0 = Clock enabled.

1 = Clock disabled.

TSIF0 Counter Clock Disable.

TSIFCNT0

0 = Clock enabled.

1 = Clock disabled.

TSIF1 Transmit Clock Disable.

TSIFTX1

0 = Clock enabled.

1 = Clock disabled.

TSIF0 Transmit Clock Disable.

TSIFTX0

0 = Clock enabled.

1 = Clock disabled.

TSIF1 Receive Clock Disable.

TSIFRX1

0 = Clock enabled.

1 = Clock disabled.

TSIF0 Receive Clock Disable.

TSIFRX0

0 = Clock enabled.

1 = Clock disabled.

CRGEN1 Clock Disable.

CRG1

0 = Clock enabled.

1 = Clock disabled.

CRGEN0 Clock Disable.

CRG0

0 = Clock enabled.

1 = Clock disabled.

Device Configurations

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